FIG. 7 is a sectional view illustrating a typical lightly doped drain field effect transistor (hereinafter referred to as LDD-FET). In FIG. 7, reference numeral 1 designates a semi-insulating GaAs substrate. A gate electrode 4, a source electrode 2, and a drain electrode 3 are disposed on the GaAs substrate 1. An n type low carrier concentration GaAs region (hereinafter referred to as n type GaAs region) 6 serving as a channel region is disposed within the GaAs substrate 1 lying below the gate electrode 4. N type high carrier concentration GaAs regions (hereinafter referred to as n.sup.+ type GaAs regions) 8a and 8b serving as source and drain regions are disposed within the GaAs substrate 1 lying below the source electrode 2 and the drain electrode 3, respectively. N type intermediate concentration GaAs regions (hereinafter referred to as n' type GaAs regions) 7 are disposed between the n.sup.+ type GaAs source and drain regions 8a and 8b surrounding the n type GaAs region 6.
FIGS. 8(a) to 8(d) are sectional views schematically illustrating a method for fabricating the LDD-FET of FIG. 7. In the figures, reference numeral 9 designates an SION film.
Initially, as illustrated in FIG. 8(a), Si ions are implanted into the semi-insulating GaAs substrate 1 to form the n type active region 6. Then, the gate electrode 4 is formed on a part of the active region 6 using a refractory metal, such as WSi (tungsten silicide).
In the step of FIG. 8(b), using the gate electrode 4 as a mask, Si ions are implanted to form the n' type region 7.
In the step of FIG. 8(c), an SiON film 9 is deposited on the gate electrode 4 and on the n' type region 7, and Si ions are implanted to form the n.sup.+ type region 8.
After removing the SiON film 9, the source and drain electrodes 2 and 3 are formed on the n.sup.+ type region 8 with a prescribed spacing, completing the LDD-FET as shown in FIG. 8(d).
FIG. 9 is a sectional view illustrating a conventional FET having a gate recess (hereinafter referred to as recessed gate FET). In FIG. 9, the same reference numerals as in FIG. 7 designate the same or corresponding parts. Reference numeral 10 designates a recess. FIGS. 10(a)-10(d) illustrate process steps for fabricating the FET of FIG. 9.
Initially, as illustrated in FIG. 10(a), Si ions are implanted into a prescribed region of a semi-insulating GaAs substrate 1 to form an n type semiconductor 6 and an n.sup.+ type semiconductor layer 8.
In the step of FIG. 10(b), source and drain electrodes 2 and 3 are formed on the n.sup.+ type semiconductor layer 8 with a prescribed spacing.
Then, a resist film (not shown) is deposited over the entire surface and an aperture is formed in a center part of the resist film. Using the resist film as a mask, portions of the semiconductor layers 6 and 8 are etched away, forming a recess 10 with a prescribed depth as shown in FIG. 10(c).
Finally, a gate electrode 4 is formed in the recess 10, completing the FET shown in FIG. 10(d).
In the above-described LDD-FET of FIG. 7 and recessed gate FET of FIG. 9, since the surface concentration of the active layer 6 is low, a surface depletion layer is thick and adversely affected by surface states, resulting in undesirable gate pulse response delay during high frequency operation, an increase in the source resistance Rs, and channel concentration at the time of large signal input. These problems will be described in detail with respect to the recessed gate FET of FIG. 11.
In FIG. 11, a high density of surface states 20 at the surface of the GaAs channel layer 6 is positioned in the center of the GaAs forbidden band and capture and emits electrons repeatedly according to variations in the gate bias V.sub.gs. The time constant of the electron emission is about several milliseconds and no electron emission follows electron capture in a high frequency band, such as a microwave band. However, since the time constant of the electron capture is significantly shorter than the time constant of the electron emission, a lot of captured electrons remain at the surface in the vicinity of the gate 4 during large amplitude operation when V.sub.gs is stationary is a high output device. Therefore, the surface depletion layer 21 in the vicinity of the gate 4 expands. If the channel layer 6 is blocked by the depletion layer 21 at the time of a transient or the like as shown in FIG. 11, the FET is unfavorably turned off. Even if the FET remains in the ON state, the depletion layer 21 causes channel concentration, i.e., the depletion layer narrows the channel between the GaAs surface and the substrate 1, resulting in poor linearity of input-output characteristics and low saturation output. Furthermore, in case of a single pulse input, so-called gate lag occurs.
FIG. 18 is a sectional view illustrating a conventional FET having a recessed gate structure. In the figure, reference numeral 21 designates a GaAs substrate. An n type active layer 22 is disposed on the GaAs substrate 1. An n.sup.+ type active layer 23 is disposed on the n type active layer 22. A source electrode 27 and a drain electrode 26 are disposed on the n.sup.+ type active layer 23 spaced apart from each other. A recess 30 is formed by etching away portions of the n type and n.sup.+ type active layers 22 and 23. A T-shaped gate structure comprising a WSi lower gate electrode 28 and an Au upper gate electrode 29 is disposed on a part of the n type active layer 22 in the recess 30. The entire surface of the structure, except the source and drain electrodes 26 and 27, is covered with SiON films 41 and 42 which are formed by CVD.
Process steps for fabricating the FET of FIG. 18 are illustrated in FIGS. 19(a)-19(h). In the figures, the same reference numerals as in FIG. 18 designate the same parts. Reference numeral 31 designates a resist film, numeral 32 designates an SiO.sub.2 film, and numeral 33 designates an SiO side wall.
Initially, ions are implanted into the GaAs substrate 21 to form the n type active layer 22 and the n.sup.+ type active layer 23. Then, an SiO.sub.2 film 32 and a resist film 31 are successively deposited on the semiconductor layer 23, and a recess pattern is formed in the resist film 31 (FIG. 19(a)).
Using the resist film 31 as a mask, a portion of the SiO.sub.2 film 32 is etched away. Then, using the resist film 31 and the SiO.sub.2 film 32 as a mask, portions of the semiconductor layers 23 and 22 are etched away to form a recess 30 having a prescribed depth (FIG. 19(b)).
After removing the resist film 31, an SiO.sub.2 film 33 is deposited in the recess 30 and on the SiO.sub.2 film 32 (FIG. 19(c)).
Then, the SiO.sub.2 film 33 is selectively etched to form side walls 33a in the recess 30 (FIG. 19(d)).
A WSi film 28 and an Au film 29 are successively deposited on the bottom surface of the recess 30, on the side walls 33a, and on the SiO.sub.2 film 32 (FIG. 19(e)).
A resist pattern 31 is formed on the Au film 29 opposite the recess 30, and the Au film 29 and the WSi film 28 are etched using the resist pattern 31 as a mask (FIG. 19(f)).
After removing the resist pattern 31, the SiO.sub.2 side walls 33a and the SiO.sub.2 film 32 are completely etched away (FIG. 19(g)).
To complete the FET, source and drain electrodes 26 and 27 are formed on the n.sup.+ type active layer 23 (FIG. 19(h)).
FIG. 20 is a sectional view of the recessed gate FET during large amplitude operation. In FIG. 20, reference numeral 35 designates a depletion layer in the OFF state of the FET, reference numeral 36 designates the depletion layer in the ON state, and numeral 37 designates the depletion layer in the transient state.
A description is given of the operation of this FET assuming that the source is grounded. When a negative voltage is applied to the gate of the FET, i.e., when the FET is in the ON state, the depletion layer extends from the gate electrode. When a positive voltage is applied to the gate, i.e., when the FET is in the OFF state, the depletion layer is reduced. Using this operation, the electric power input to the gate electrode (28 and 29) is amplified and drained from the drain electrode 27. During the high frequency and large amplitude operation, however, since electrons are captured by the surface states at the GaAs surface, the depletion layer opposite the gate electrode expands and the channel is narrowed.
In the above-described LDD-FET and recessed gate FETs, since the surface concentration of the active layer is low, the surface depletion layer is thick and adversely affected by the surface states, resulting in undesirable gate pulse response delay during high frequency operation, increase in the source resistance Rs, and channel concentration at the time of large signal input. Particularly during the high frequency and large amplitude operation, the channel concentration adversely affects the linearity of input-output characteristics and reduces the saturation power. Further, the gate lag, which occurs at the time of single pulse input, becomes considerable.